计组课设: 设计一台嵌入式CISC模型计算机

课程设计题目及要求

课程名: 计算机组成原理
题目: 设计一台嵌入式CISC模型计算机
要求:
  采用定长CPU周期、联合控制方式,并运行能完成一定功能的机器语言源程序进行验证,机器语言源程序功能如下:

输入包含5个整数(有符号数)的数组M,输出所有负数的立方和。

  嵌入式模型计算机内必须设计和使用RAM存储器读写数据,相应地需要设计对RAM存储器数据的读写指令,以及对RAM中数组操作必须的寄存器间接寻址方式等。

系统总体设计

一、数据通路设计

图1 CISC模型机数据通路框图

二、微程序控制器设计

图2 微程序控制器逻辑结构框图

说明:
  在T4内形成微指令的微地址,并访问控制存储器,在T2的上边沿到来时,将读出的微指令打入微指令寄存器,即图中的微命令寄存器和微地址寄存器。

指令系统设计

一、机器指令设计

图3 机器指令表

二、微指令设计
CISC模型机系统使用的微指令采用全水平型微指令,字长为26位,其中微命令字段为18位,P字段为2位,后继微地址为6位。

图4 微指令格式

图5 微指令表

单元电路设计

一、顶层电路图
二、微程序控制器CONTROL_UNIT

VHDL代码

折叠
一、ADDR

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ADDR IS
PORT(
	I3,I2,I1,I0:IN STD_LOGIC;
	CF,ZF,T4,P2,P1:IN STD_LOGIC;
	SE5,SE4,SE3,SE2,SE1,SE0:OUT STD_LOGIC
	);
END ADDR;

ARCHITECTURE A OF ADDR IS
BEGIN
	SE5<='1';
	SE4<=NOT(CF AND (NOT ZF) AND P2 AND T4);
	SE3<=NOT(I3 AND P1 AND T4);
	SE2<=NOT(I2 AND P1 AND T4);
	SE1<=NOT(I1 AND P1 AND T4);
	SE0<=NOT(I0 AND P1 AND T4);
END A;

二、ALU

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY ALU IS
PORT(
	X:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	Y:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	S2,S1,S0:IN STD_LOGIC;
	ALUOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	CF,ZF:OUT STD_LOGIC
	);
END ALU;

ARCHITECTURE A OF ALU IS
SIGNAL RESULT:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
	PROCESS
	BEGIN
		IF(S2='0' AND S1='0' AND S0='0')THEN	--ADD
			RESULT<=('0'&X)+('0'&Y);
			ALUOUT<=RESULT(7 DOWNTO 0);
			CF<=RESULT(8);
			IF(RESULT="100000000" OR RESULT="000000000") THEN
				ZF<='1';
			ELSE
				ZF<='0';
			END IF;
		ELSIF(S2='0' AND S1='0' AND S0='1')THEN	--IMUL
			RESULT<=('0'&X)*('0'&Y);
			ALUOUT<=RESULT(7 DOWNTO 0);
			CF<=RESULT(8);
			IF(RESULT="100000000" OR RESULT="000000000")THEN
				ZF<='1';
			ELSE
				ZF<='0';
			END IF;
		ELSIF(S2='0' AND S1='1' AND S0='0') THEN	--INC
			RESULT<=Y+1;
			ALUOUT<=RESULT(7 DOWNTO 0);
			CF<=RESULT(8);
			IF(RESULT="000000000" OR RESULT="100000000") THEN
				ZF<='1';
			ELSE
				ZF<='0';
			END IF;

		ELSIF(S2='0' AND S1='1' AND S0='1') THEN	--DEC
			RESULT<=Y-1;
			ALUOUT<=RESULT(7 DOWNTO 0);
			CF<=RESULT(8);
			IF(RESULT="000000000" OR RESULT="100000000") THEN
				ZF<='1';
			ELSE
				ZF<='0';
			END IF;
		ELSIF(S2='1' AND S1='0' AND S0='0') THEN	--CMP
			ALUOUT<=X-Y;
			IF(XBUS)
			ALUOUT<=Y;
			CF<='0';
			ZF<='0';
		ELSE
			ALUOUT<="00000000";
			CF<='0';
			ZF<='0';
		END IF;
	END PROCESS;
END A;

三、CONTROM

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CONTROM IS
PORT(
	ADDR:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
	UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
	D:OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
	);
END CONTROM;

ARCHITECTURE A OF CONTROM IS
SIGNAL DATAOUT:STD_LOGIC_VECTOR(25 DOWNTO 0);
BEGIN
	PROCESS(ADDR)
	BEGIN
		CASE ADDR IS
            WHEN "000000" => DATAOUT<="11010010001111110110000000";--(OP->IR,PC+1)
			WHEN "000001" => DATAOUT<="10001010001011111100000000";--IN
			WHEN "000010" => DATAOUT<="10000000001101111100000000";--OUT
			WHEN "000011" => DATAOUT<="10001010001111111000000000";--MOV
			WHEN "000100" => DATAOUT<="10001000001111111100000000";--MOVS
			WHEN "000101" => DATAOUT<="10100011010111111100001101";--STOI
			WHEN "000110" => DATAOUT<="10100000001111111100001110";--LAD
			WHEN "000111" => DATAOUT<="10001110000111111100000000";--ADD
			WHEN "001000" => DATAOUT<="10001110010111111100000000";--IMUL
			WHEN "001001" => DATAOUT<="10001110100111111100000000";--INC
			WHEN "001010" => DATAOUT<="10001110110111111100000000";--DEC
			WHEN "001011" => DATAOUT<="10000111001111111100000000";--CMP
			WHEN "001100" => DATAOUT<="10000010001111111101000000";--JB
            WHEN "001101" => DATAOUT<="10000000001110011100000000";--(Rs->DBUS,WE,RAM)
            WHEN "001110" => DATAOUT<="10001010001111001100000000";--(RD,RAM,DBUS-Rd)
			WHEN "010000" => DATAOUT<="01000010001111111000000000";--(IR(A)-PC)
			WHEN OTHERS   => DATAOUT<="00000000000000000000000000";
		END CASE;
		UA(5 DOWNTO 0)<=DATAOUT(5 DOWNTO 0);
		D(19 DOWNTO 0)<=DATAOUT(25 DOWNTO 6);
	END PROCESS;
END A;

四、CONVERT

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CONVERT IS
PORT(
	IRCODE:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	OP:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	I11,I10,I9,I8:OUT STD_LOGIC;
	A:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END CONVERT;

ARCHITECTURE A OF CONVERT IS
BEGIN
	OP<=IRCODE(15 DOWNTO 12);
	I11<=IRCODE(11);
	I10<=IRCODE(10);
	I9<=IRCODE(9);
	I8<=IRCODE(8);
	A<=IRCODE(7 DOWNTO 0);
END A;

五、COUNTER

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNTER IS
PORT(
	CLK,CLR:IN STD_LOGIC;
	T4,T3,T2:OUT STD_LOGIC
	);
END COUNTER;

ARCHITECTURE A OF COUNTER IS
SIGNAL X:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
	PROCESS(CLK,CLR)
	BEGIN
		IF(CLR='0')THEN
			X<="00";
			T4<='0';
			T3<='0';
			T2<='0';
		ELSIF(CLK'EVENT AND CLK='1') THEN
			X<=X+1;
			T4<=X(1) AND X(0);
			T3<=X(1) AND (NOT X(0));
			T2<=(NOT X(1)) AND X(0);
		END IF;
	END PROCESS;
END A;

六、DECODER

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DECODER IS
PORT(
	I9,I8:IN STD_LOGIC;
	Y3,Y2,Y1,Y0:OUT STD_LOGIC
	);
END DECODER;

ARCHITECTURE A OF DECODER IS
BEGIN
	PROCESS
	BEGIN
		IF(I9='0' AND I8='0')THEN
			Y3<='0';
			Y2<='0';
			Y1<='0';
			Y0<='1';
		ELSIF(I9='0' AND I8='1')THEN
			Y3<='0';
			Y2<='0';
			Y1<='1';
			Y0<='0';
		ELSIF(I9='1' AND I8='0')THEN
			Y3<='0';
			Y2<='1';
			Y1<='0';
			Y0<='0';
		ELSE
			Y3<='1';
			Y2<='0';
			Y1<='0';
			Y0<='0';
		END IF;
	END PROCESS;
END A;

七、F1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F1 IS
PORT(
        UA5,UA4,UA3,UA2,UA1,UA0:IN STD_LOGIC;
        D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END F1;

ARCHITECTURE A OF F1 IS
BEGIN
        D(5)<=UA5;
        D(4)<=UA4;
        D(3)<=UA3;
        D(2)<=UA2;
        D(1)<=UA1;
        D(0)<=UA0;
END A;

八、F2

LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F2 IS 
PORT(
    D:IN STD_LOGIC_VECTOR(5 DOWNTO 0);
    UA5,UA4,UA3,UA2,UA1,UA0: OUT STD_LOGIC
    );
END F2;

ARCHITECTURE A OF F2 IS
BEGIN
    UA5<=D(5);
    UA4<=D(4);
    UA3<=D(3);
    UA2<=D(2);
    UA1<=D(1);
    UA0<=D(0);
END A;

九、F3

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY F3 IS 
PORT(
    D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    I3,I2,I1,I0: OUT STD_LOGIC
    );
END F3;

ARCHITECTURE A OF F3 IS
BEGIN
    I3<=D(3);
    I2<=D(2);
    I1<=D(1);
    I0<=D(0);
END A;

十、FEN2

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FEN2 IS
PORT(
	LED_B:IN STD_LOGIC;
	DBUS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	FENOUT,OUTBUS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END FEN2;

ARCHITECTURE A OF FEN2 IS
BEGIN
	PROCESS
	BEGIN
		IF(LED_B='0') THEN
			OUTBUS<=DBUS;
		ELSE
			FENOUT<=DBUS;
		END IF;
	END PROCESS;
END A;

十一、IR

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY IR IS
PORT(
	D:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	CLK:IN STD_LOGIC;
	O:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END IR;

ARCHITECTURE A OF IR IS
BEGIN
	PROCESS(CLK)
	BEGIN
		IF(CLK'EVENT AND CLK='1')THEN
			O<=D;
		END IF;
	END PROCESS;
END A;

十二、LS273

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PSW IS
PORT(
	CF_IN,ZF_IN:IN STD_LOGIC;
	CF,ZF:OUT STD_LOGIC;
	LDPSW:IN STD_LOGIC
	);
END PSW;

ARCHITECTURE A OF PSW IS
BEGIN
	PROCESS(LDPSW)
	BEGIN
		IF(LDPSW'EVENT AND LDPSW='1') THEN
			CF<=CF_IN;
			ZF<=ZF_IN;
		END IF;
	END PROCESS;
END A;

十三、MCOMMAND

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY MCOMMAND IS
PORT(
	T4,T3,T2:IN STD_LOGIC; 
	O:IN STD_LOGIC_VECTOR(19 DOWNTO 0);
     P2,P1,LOAD,LDPC,LDAR,LDIR,LDRI,LDPSW,RS_B,S2,S1,S0,ALU_B,SW_B,LED_B,RD_D,CS_D,RAM_B,CS_I,ADDR_B:OUT STD_LOGIC 
    );
END  MCOMMAND;
ARCHITECTURE A OF MCOMMAND IS
SIGNAL DATAOUT:STD_LOGIC_VECTOR(19 DOWNTO 0);
BEGIN 
	PROCESS(T2)
    	BEGIN
      		IF(T2'EVENT AND T2='1') THEN
     			DATAOUT(19 DOWNTO 0)<=O(19 DOWNTO 0);
        	END IF;
        	LOAD<=DATAOUT(19);
        	LDPC<=DATAOUT(18) AND T4;
        	LDAR<=DATAOUT(17) AND T3;
        	LDIR<=DATAOUT(16) AND T3;
        	LDRI<=DATAOUT(15) AND T4;
        	LDPSW<=DATAOUT(14) AND T4;
        	RS_B<=DATAOUT(13);
        	S2<=DATAOUT(12);
        	S1<=DATAOUT(11);
        	S0<=DATAOUT(10);
        	ALU_B<=DATAOUT(9);
        	SW_B<=DATAOUT(8);
        	LED_B<=DATAOUT(7);
        	RD_D<=NOT(NOT DATAOUT(6) AND (T2 OR T3));
        	CS_D<=NOT(NOT DATAOUT(5) AND T3);
        	RAM_B<=DATAOUT(4);
        	CS_I<=DATAOUT(3);
        	ADDR_B<=DATAOUT(2);
        	P1<=DATAOUT(1);
        	P2<=DATAOUT(0);
    	END PROCESS;
END A;

十四、MMM

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MMM IS
PORT(
	SE:IN STD_LOGIC;
	CLK:IN STD_LOGIC;
	D:IN STD_LOGIC;
	CLR:IN STD_LOGIC;
	UA:OUT STD_LOGIC
	);
END MMM;

ARCHITECTURE A OF MMM IS
BEGIN
	PROCESS(CLR,SE,CLK)
	BEGIN
		IF(CLR='0')THEN
			UA<='0';
		ELSIF(SE='0')THEN
			UA<='1';
		ELSIF(CLK'EVENT AND CLK='1')THEN
			UA<=D;
		END IF;
	END PROCESS;
END A;

十五、MUX3_1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX3_1 IS
PORT(
	INBUS,RAMOUT,FEN2OUT:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	SW_B,RAM_B:IN STD_LOGIC;
	DBUS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END MUX3_1;

ARCHITECTURE A OF MUX3_1 IS
BEGIN
	PROCESS
	BEGIN
		IF(SW_B='0')THEN
			DBUS<=INBUS;
		ELSIF(RAM_B='0')THEN
			DBUS<=RAMOUT;
		ELSE
			DBUS<=FEN2OUT;
		END IF;
	END PROCESS;
END A;

十六、MUX3_2

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX3_2 IS
PORT(
	ALUOUT,RSOUT,AOUT:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	ALU_B,RS_B,ADDR_B:IN STD_LOGIC;
	DBUS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END MUX3_2;

ARCHITECTURE A OF MUX3_2 IS
BEGIN
	PROCESS
	BEGIN
		IF(ALU_B='0')THEN
			DBUS<=ALUOUT;
		ELSIF(RS_B='0')THEN
			DBUS<=RSOUT;
		ELSIF(ADDR_B='0')THEN
			DBUS<=AOUT;
		ELSE
			DBUS<="00000000";
		END IF;
	END PROCESS;
END A;

十七、MUX4_1

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX4_1 IS
PORT(
	R3,R2,R1,R0:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	I11,I10:IN STD_LOGIC;
	X:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END MUX4_1;

ARCHITECTURE A OF MUX4_1 IS
BEGIN 
	PROCESS
	BEGIN
       IF(I11='0' AND I10='0') THEN     			
            X<=R0;
	   ELSIF(I11='0' AND I10='1')THEN 
			X<=R1;			
	   ELSIF(I11='1' AND I10='0')THEN 
			X<=R2;			
	   ELSIF(I11='1' AND I10='1')THEN 
			X<=R3;
	   END IF;
	END PROCESS;
END A;

十八、MUX4_2

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX4_2 IS
PORT(
	R3,R2,R1,R0:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	I9,I8:IN STD_LOGIC;
	Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END MUX4_2;

ARCHITECTURE A OF MUX4_2 IS
BEGIN 
	PROCESS
	BEGIN
       IF(I9='0' AND I8='0') THEN     			
            Y<=R0;
	   ELSIF(I9='0' AND I8='1')THEN 
			Y<=R1;			
	   ELSIF(I9='1' AND I8='0')THEN 
			Y<=R2;			
	   ELSIF(I9='1' AND I8='1')THEN 
			Y<=R3;
	   END IF;
	END PROCESS;
END A;

十九、PC

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PC IS
PORT(
	LOAD,LDPC,CLR:IN STD_LOGIC;
	D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END PC;

ARCHITECTURE A OF PC IS
SIGNAL QOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	PROCESS(LDPC,CLR,LOAD)
	BEGIN
		IF(CLR='0')THEN
			QOUT<="00000000";
		ELSIF(LDPC'EVENT AND LDPC='1')THEN
			IF(LOAD='0')THEN
				QOUT<=D;
			ELSE
				QOUT<=QOUT+1;
			END IF;
		END IF;
	END PROCESS;
	O<=QOUT;
END A;

二十、PSW

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PSW IS
PORT(
	CF_IN,ZF_IN:IN STD_LOGIC;
	CF,ZF:OUT STD_LOGIC;
	LDPSW:IN STD_LOGIC
	);
END PSW;

ARCHITECTURE A OF PSW IS
BEGIN
	PROCESS(LDPSW)
	BEGIN
		IF(LDPSW'EVENT AND LDPSW='1') THEN
			CF<=CF_IN;
			ZF<=ZF_IN;
		END IF;
	END PROCESS;
END A;

二十一、RAM

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RAM IS
PORT(
	RD_D,CS_D:IN STD_LOGIC;
	DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END RAM;

ARCHITECTURE A OF RAM IS
TYPE MEMORY IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	PROCESS(CS_D)
	VARIABLE MEM:MEMORY;
	BEGIN
		IF(CS_D'EVENT AND CS_D='0') THEN
			IF(RD_D='0') THEN
				MEM(CONV_INTEGER(ADDR(4 DOWNTO 0))):=DIN;
			ELSE
				DOUT<=MEM(CONV_INTEGER(ADDR(4 DOWNTO 0)));
			END IF;
		END IF;
	END PROCESS;
END A;

二十二、ROM

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ROM IS
PORT(
	DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
	ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	CS_I:IN STD_LOGIC
	);
END ROM;

ARCHITECTURE A OF ROM IS
BEGIN
DOUT <=
"0011000100000000" WHEN ADDR="00000000" AND CS_I = '0' ELSE	--MOV	R1,00H
"0011001000000101" WHEN ADDR="00000001" AND CS_I = '0' ELSE	--MOV	R2,05H
"0011001100000000" WHEN ADDR="00000010" AND CS_I = '0' ELSE	--MOV	R3,00H
"0001000000000000" WHEN ADDR="00000011" AND CS_I = '0' ELSE	--IN		R0 
"1011110000000000" WHEN ADDR="00000100" AND CS_I = '0' ELSE	--CMP	R3,R0
"1100000000001000" WHEN ADDR="00000101" AND CS_I = '0' ELSE	--JB		08H
"0101000100000000" WHEN ADDR="00000110" AND CS_I = '0' ELSE	--STOI	R0,[R1]
"1001000100000000" WHEN ADDR="00000111" AND CS_I = '0' ELSE	--INC	R1
"1010001000000000" WHEN ADDR="00001000" AND CS_I = '0' ELSE	--DEC	R2
"1011111000000000" WHEN ADDR="00001001" AND CS_I = '0' ELSE	--CMP	R3,R2
"1100000000000011" WHEN ADDR="00001010" AND CS_I = '0' ELSE	--JB		03H
"0100011000000000" WHEN ADDR="00001011" AND CS_I = '0' ELSE	--MOVS	R1,R2
"1010001000000000" WHEN ADDR="00001100" AND CS_I = '0' ELSE	--DEC	R2
"0011000100000000" WHEN ADDR="00001101" AND CS_I = '0' ELSE	--MOV	R1,00H
"0110100000000000" WHEN ADDR="00001110" AND CS_I = '0' ELSE	--LAD	[R2],R0
"0110101100000000" WHEN ADDR="00001111" AND CS_I = '0' ELSE	--LAD	[R2],R3
"1000000000000000" WHEN ADDR="00010000" AND CS_I = '0' ELSE	--IMUL	R0,R0
"1000110000000000" WHEN ADDR="00010001" AND CS_I = '0' ELSE	--IMUL	R3,R0
"0100000100000000" WHEN ADDR="00010010" AND CS_I = '0' ELSE	--MOVS	R0,R1
"1010001000000000" WHEN ADDR="00010011" AND CS_I = '0' ELSE	--DEC	R2
"0110100000000000" WHEN ADDR="00010100" AND CS_I = '0' ELSE	--LAD	[R2],R0
"0110101100000000" WHEN ADDR="00010101" AND CS_I = '0' ELSE	--LAD	[R2],R3
"1000000000000000" WHEN ADDR="00010110" AND CS_I = '0' ELSE	--IMUL	R0,R0
"1000110000000000" WHEN ADDR="00010111" AND CS_I = '0' ELSE	--IMUL	R3,R0
"0111010000000000" WHEN ADDR="00011001" AND CS_I = '0' ELSE	--ADD	R1,R0
"0100000100000000" WHEN ADDR="00011010" AND CS_I = '0' ELSE	--MOVS	R0,R1
"0011001100000000" WHEN ADDR="00011011" AND CS_I = '0' ELSE	--MOV	R3,00H
"1011111000000000" WHEN ADDR="00011100" AND CS_I = '0' ELSE	--CMP	R3,R2
"1100000000010011" WHEN ADDR="00011101" AND CS_I = '0' ELSE	--JB		13H
"0010010000000000" WHEN ADDR="00011110" AND CS_I = '0' ELSE	--OUT	R1
"0000000000000000";
END A;
点赞

发表评论

电子邮件地址不会被公开。必填项已用 * 标注

隐藏
变装